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advance data sheet 1 lh7a404 advance data sheet 32-bit system-on-chip features ? arm922t? core: ? 32-bit arm9tdmi? risc core (200 mhz) ? 16kb cache: 8kb instruction cache and 8kb data cache ? mmu (windows ce? enabled) 80kb on-chip memory vectored interrupt controller external bus interface ? 100 mhz ? asynchronous sram/rom/flash ? synchronous dram/flash ? pcmcia ? compact flash clock and power management ? 32.768 khz and 14. 7456 mhz oscillators ? programmable pll low power modes ? run (200 ma), halt, standby (35 a) programmable lcd controller ? up to 1,024 768 resolution ? supports stn, colo r stn, hr-tft, tft ? up to 64 k-colors and 15 gray shades 10 channel, 10-bit a/d converter ? touch screen controller ? brownout detector dma (12 channels) ? external dma channels ? aac (ac97) ?mmc ?usb usb host and device interface (usb1.1) synchronous serial port (ssp) ? motorola spi? ? texas instruments ssi ? national microwire? ps/2 keyboard/mouse interface (kmi) three programmable timers three uarts ? classic irda (115 kbit/s) smart card interface (iso7816) four pulse width modulators (pwms) multimediacard interface with secure digital (mmc 2.11/sd 1.0) aac (ac97) codec interface smart battery monitor interface real time clock (rtc) up to 64 general purpose i/o channels programmable interrupt controller watchdog timer jtag debug interface and boundary scan operating voltage ? 1.8 v core ? 3.3 v input/output (1.8 v i/o optional*) temperature ? 0c to +70c commercial ? -40c to +85c industrial (with clock frequency reduction*) 324-ball pbga package description the advent of 3g technology opens the door for a wide range of multimedia applications in mobile infor- mation appliances. these appliances require high pro- cessing performance and low power consumption. the lh7a404 is designed from the ground up to provide high processing performance, low power consumption, and a high level of integration. the lh7a404 contains a high performance 32-bit arm922t core. power consumption is reduced by the high level of integration, 80kb on-chip sram, fully static design, power management unit, low voltage operation (1.8 v core, 1.8 v or 3.3 v i/o) and on-chip pll. motorola spi is a trademark of motorola, inc. national semiconductor microwire is a trademark of national semiconductor corporation. arm922t and arm 9tdmi are trademar ks of advanced risc machines (arm) ltd. windows ce is a trademark of microsoft corporation. note: *under development. results pending further characterization.
lh7a404 32-bit system-on-chip 2 advance data sheet figure 1. lh7a404 block diagram lh7a404-1 oscillator, pll1 and pll2, power management, and reset control vectored interrupt controller real time clock 14.7456 mhz 32.768 khz synchronous memory controller pcmcia/cf controller color lcd controller 80kb sram lcd ahb bus asynchronous memory controller external bus interface arm 922t advanced peripheral bus bridge dma controller advanced high-performance bus (ahb) advanced perpheral bus (apb) hr-tft lcd timing controller usb host interface general purpose i/o (64) synchronous serial port timer (3) battery monitor interface usb device interface watchdog timer irda interface uart (3) multimedia card/ secure digital interface smart card interface (iso7816) pwm (4) ps/2 interface a/d touch screen controller codec interface ac97 color lcd controller
32-bit system-on-chip lh7a404 advance data sheet 3 table 1. functional pin list bga signal description output drive j9 vdd i/o ring power k9 m9 n9 p9 p11 p12 p13 p14 n14 m14 l14 k14 j14 j13 j11 j10 e4 vss i/o ring ground h4 l4 r4 w8 w11 w15 w19 t19 p19 m19 k19 g19 d18 d14 d10 d7 k3 vddc core power y5 y12 v20 n20 h20 d20 c12 c8 f3
lh7a404 32-bit system-on-chip 4 advance data sheet g2 vssc core ground m2 aa6 aa15 p21 k21 f21 b17 b10 b5 aa17 vdda1 analog power for pll1 ab17 vssa1 analog ground for pll1 aa18 vdda2 analog power for pll2 ab18 vssa2 analog ground for pll2 ab16 vdda3 analog power for a/d, touch screen controller ab13 vssa3 analog ground for a/d, touch screen controller d3 npor power on reset e3 nureset user reset d4 wakeup wake up e1 npwrfl power fail signal 2 ma c2 nextpwr external power aa16 xtalin 14.7456 mhz crystal oscillator pins. to drive the device from an external clock source, xtalin can be used while xtalout is left unconnected. y16 xtalout aa21 xtal32in 32.768 khz real time clock, cryst al oscillator pins. to drive the device fr om an external clock source, xtal32in can be used while xtal32out is left unconnected. y20 xtal32out l3 pgmclk programmable clock (14.7456 mhz max.) 8 ma ab22 ncs0 asynchronous memory chip select 0 (rom/flash) 16 ma n13 ncs1 asynchronous memory chip select 1 16 ma y21 ncs2 asynchronous memory chip select 2 16 ma w20 ncs3/nmmcsel asynchronous memory chip select 3 and mmc select 16 ma y22 ncs6 asynchronous memory chip select 6 16 ma w21 ncs7 asynchronous memory chip select 7 16 ma table 1. functional pin list (cont?d) bga signal description output drive
32-bit system-on-chip lh7a404 advance data sheet 5 w22 d0 data bus 16 ma v21 d1 u22 d2 u20 d3 t22 d4 t20 d5 r21 d6 r19 d7 p20 d8 n21 d9 m22 d10 m20 d11 l21 d12 l19 d13 k20 d14 j21 d15 j19 d16 h21 d17 g22 d18 g20 d19 f20 d20 e22 d21 e20 d22 d22 d23 c22 d24 b22 d25 b21 d26 d19 d27 b20 d28 a20 d29 b19 d30 b18 d31 a1 tdi jtag data in. this signal should be pulled-up to vdd v22 a0 address bus 16 ma v19 a1 u21 a2/sa0 address bus and synchronous address bus 16 ma u19 a3/sa1 t21 a4/sa2 r22 a5/sa3 r20 a6/sa4 p22 a7/sa5 n22 a8/sa6 n19 a9/sa7 m21 a10/sa8 l22 a11/sa9 l20 a12/sa10 k22 a13/sa11 j22 a14/sa12 j20 a15/sa13 table 1. functional pin list (cont?d) bga signal description output drive
lh7a404 32-bit system-on-chip 6 advance data sheet h22 a16/sbank0 address bus and synchronous bank 0 16 ma h19 a17/sbank1 address bus and synchronous bank 1 16 ma g21 a18 address bus 16 ma f22 a19 f19 a20 e21 a21 e19 a22 d21 a23 c21 a24 a18 a25 a17 a26 c17 a27 c14 noe asynchronous memory output enable 16 ma a13 nwe0 asynchronous memory write enable 0 16 ma m13 nwait asynchronous memory controller wait a16 scken3 clock enable 3 fo r synchronous memory 16 ma b16 sclk synchronous memory clock 2 24 ma c16 scke1 clock enable 1 fo r synchronous memory 16 ma d16 scke0 clock enable 0 fo r synchronous memory 16 ma a22 nscs0 synchronous memory chip select 0 16 ma c20 nscs1 synchronous memory chip select 1 16 ma a21 nscs2 synchronous memory chip select 2 16 ma c19 nscs3 synchronous memory chip select 3 16 ma a19 nswe synchronous memory write enable 16 ma m3 pa0/lcdvd16 gpio port a and lcd data pins 16 and 17 8 ma m1 pa1/lcdvd17 n4 pa2 gpio port a 8 ma n3 pa3 n2 pa4 n1 pa5 p4 pa6 p3 pa7 p2 pb0/uartrxd1 gpio port b and uart1 receive data input 8 ma l10 pb1/uarttxd3 gpio port b and uart3 transmit data out 8 ma l11 pb2/uartrxd3 gpio port b and uart3 receive data in 8 ma m10 pb3/uartcts3 gpio port b and uart3 clear to send 8 ma m11 pb4/uartdcd3 gpio port b and uart3 data carrier detect 8 ma n10 pb5/uartdsr3 gpio port b and uart3 data set ready 8 ma p1 pb6/bmiswib/bmismbio gpio port b and battery monitor interface 8 ma r1 pb7/bmismbclk r2 pc0/txd1 gpio port c and uart1 transmit data output 16 ma r3 pc1 gpio port c 16 ma t1 pc2 gpio port c 16 ma t2 pc3 gpio port c 16 ma t3 pc4 gpio port c 16 ma t4 pc5 gpio port c 16 ma u1 pc6 gpio port c 16 ma u2 pc7 gpio port c 16 ma table 1. functional pin list (cont?d) bga signal description output drive
32-bit system-on-chip lh7a404 advance data sheet 7 ab10 pd0/lcdvd8 gpio port d and lcd video data interface 16 ma aa10 pd1/lcdvd9 y10 pd2/lcdvd10 w10 pd3/lcdvd11 ab11 pd4/lcdvd12 aa11 pd5/lcdvd13 y11 pd6/lcdvd14 ab12 pd7/lcdvd15 aa8 pe0/lcdvd4 gpio port e and lcd video data interface 16 ma aa9 pe1/lcdvd5 y9 pe2/lcdvd6 w9 pe3/lcdvd7 c4 pe4 gpio port e 16 ma a3 pe5 b3 pe6 a2 pe7 l13 pf0 gpio port f and smart card interface. can be used for external interrupts. interrupts can be level or edge tri ggered and are internally debounced. 8 ma k13 pf1 l12 pf2 k12 pf3 j12 pf4 k11 pf5/scidetect c10 pf6 a9 pf7 w4 pg0/ncfoe gpio port g/compact flash output enable 8 ma aa1 pg1/ncfwe gpio port g/compact flash write enable 8 ma aa2 pg2/ncfiord gpio port g/compact flash i/o read strobe 8 ma ab1 pg3/ncfiowr gpio port g/compact flash i/o write strobe 8 ma ab2 pg4/ncfreg gpio port g/compact flash register memory access 8 ma aa3 pg5/ncfce1 gpio port g/compact flash chip enable 1 8 ma ab3 pg6/ncfce2 gpio port g/compact flash chip enable 2 8 ma y3 pg7/pcdir gpio port g/pc card direction 8 ma ab4 ph0/cfreseta gpio port h/compact flash reset a 8 ma aa4 ph1/cfa8/cfa24/ cfresetb gpio port h/compact flash address bit 8/ pcmcia1 address bit 24/pcmcia2 reset b 8 ma y4 ph2/ncfena gpio port h/compact flash enable a 8 ma ab5 ph3/cfa9/cfa25/ncfenb gpio port h/compact flash address bit 9/pc mcia1 address bit 25/pcmcia2 enable b 8 ma aa5 ph4/ncfwait/ncfwaita gpio port h/compact flash wait signal/pcmcia wait a 8 ma w5 ph5/cfa10/ncfwaitb gpio port h/compact flash address bit 10/pcmcia2 wait b 8 ma ab6 ph6/ac97reset gpio port h/ac97 reset 8 ma y6 ph7/ncfstaten gpio port h/compact flash status read enable 8 ma u3 lcdfp/lcdsps lcd frame pulse / hr-tft reset row driver counter 16 ma v1 lcdlp/lcdhrlp lcd linepulse / hr-tft latch pulse 16 ma u4 lcdcls hr-tft clock for row drivers 16 ma v2 lcdspl hr-tft start pulse left for reverse scanning 16 ma v3 lcdubl hr-tft up, down signal for reverse scanning 16 ma v4 lcdspr hr-tft start pulse right for normal scanning 16 ma w1 lcdlbr hr-tft output for reverse scanning 16 ma table 1. functional pin list (cont?d) bga signal description output drive
lh7a404 32-bit system-on-chip 8 advance data sheet w2 lcdmod hr-tft mod signal used by the row driver 16 ma w3 lcdps hr-tft power save 16 ma y1 lcdclpower hr-tft power sequence control 16 ma y2 lcdrev hr-tft reverse 16 ma w6 lcdclkin external clock input for lcd controller aa7 lcdvd0 lcd video data interface 16 ma y7 lcdvd1 w7 lcdvd2 ab8 lcdvd3 p10 lcdm ac bias for lcd. this si gnal is used on stn displays 16 ma ab9 lcddclk lcd pixel clock 16 ma w17 usbdcp usb device control y18 usbdp usb data positive (differential pair) w18 usbdn usb data negative (differential pair) ab19 usbhdp0 usb data host positive 0 (differential pair) aa19 usbhdn0 usb data host negative 0 (differential pair) ab20 usbhdp1 usb data host positive 1(differential pair) aa20 usbhdn1 usb data host negative 1(differential pair) y19 usbhpwr usb host power ab21 usbhovrcurr usb overcurrent b12 pwmen0 dc-dc converter 0 enable 8 ma d12 pwmen1 dc-dc converter 1 enable 8 ma a11 pwm0 dc-dc converter 0 output (pulse width modulated) 8 ma b11 pwm1 dc-dc converter 1 output (pulse width modulated) 8 ma c11 pwm2 pwm output 2 8 ma d11 pwm3 pwm output 3 8 ma a10 pwmsync0 pwm synchronizing input b9 ac97clk ac97 codec clock (aac/normal) 8 ma c9 ac97out ac97 codec output (aac/normal) 8 ma d9 ac97sync ac97 codec sync (aac/normal) 8 ma a8 ac97in ac97 codec input (aac/normal) 8 ma b8 mmcclk/spiclk multimediacard clock (20 mhz max.)/optional spi mode clock 8 ma d8 mmccmd/spidi multimediacard command/optional spi mode data in 8 ma a7 mmcdata0/spido multimediacard data/optional spi mode data out 8 ma b7 mmcdata1 multimediacard data 1 8 ma c7 mmcdata2 multimediacard data 2 8 ma a6 mmcdata3 multimediacard data 3 8 ma f4 uartcts2 uart2 clear to send signal 8 ma e2 uartdcd2 uart2 data carrier detect signal 8 ma k10 uartdsr2 uart2 data send ready signal 8 ma f2 uarttx1/uartirtx1 uart1 transmit / irda transmit 8 ma f1 uartrx1/uartirrx1 uart1 receive / irda receive 8 ma g4 uarttxd2 uart2 transmit data output 8 ma g3 uartrxd2 uart2 receive data input 8 ma k1 sspclk synchronous serial port clock 8 ma l2 ssprx synchronous serial port receive 8 ma l1 ssptx synchronous serial port transmit 8 ma m4 sspfrm synchronous serial port frame sync 8 ma table 1. functional pin list (cont?d) bga signal description output drive
32-bit system-on-chip lh7a404 advance data sheet 9 h2 col0 keyboard interface 8 ma h1 col1 j4 col2 j3 col3 j2 col4 j1 col5 k4 col6 k2 col7 b1 tclk jtag clock. this signal should be pulled-up to vdd b2 tdo jtag data out 4 ma c1 tmst jtag test mode select. this signal should be pulled-up to vdd c3 medchg media change for smart card interface d1 batok battery ok d2 nbatchg battery change g1 kmidat keyboard / mouse data 16 ma h3 kmiclk keyboard /mouse clock 16 ma l9 buz buzzer output (254 khz max.) 8 ma ab7 nble2 byte lane enable 2 16 ma y8 nble1 byte lane enable 1 16 ma aa12 batcntl battery control for a/d controller battery monitor. 16 ma n11 bootwidth0 boot width pins. used with the medchg bit. on power up, the values on these pins are latched to determine the width and type of boot device. boot width c an be 8-, 16-, or 32-bit. n12 bootwidth1 w12 lr_ym touch screen controller lower right y-minus aa13 an1 a/d channel 1 y13 an6 a/d channel 6 w13 ll_yp touch screen controller lower left y-plus ab14 an5 a/d channel 5 aa14 an2 a/d channel 2 y14 ur_xm touch screen controller upper right x-minus w14 an4 a/d channel 4 ab15 an3 a/d channel 3 y15 ul_xp touch screen controller upper left x-plus, w16 ntest0 test pins. tie to vdd. y17 ntest1 aa22 oscen oscillator enable output 8 ma c18 ncas column address strobe signal 16 ma d17 nras row address strobe signal 16 ma a15 nble3 byte lane enable 3 8 ma b15 nble0 byte lane enable 0 8 ma c15 dqm0 data mask for synchronous memories 16 ma d15 dqm1 a14 dqm2 b14 dqm3 b13 sciio smart card interface i/o 16 ma c13 sciclk smart card interface clock 16 ma d13 scireset smart card interface reset 16 ma a12 scivccen smart card interface vcc enable 16 ma table 1. functional pin list (cont?d) bga signal description output drive
lh7a404 32-bit system-on-chip 10 advance data sheet notes: 1. signals beginning with ?n? are active low. 2. the sclk pin can source up to 16 ma and sink up to 24 ma. see ?dc characteristics?. notes: 1. the intensity bit is identical ly generated for all three colors. 2. mu = monochrome upper 3. cu = color upper 4. cl = color lower b6 ctclkin counter timer clock input c6 nresetout reset output to external devices 16 ma d6 dreq0 dma request 0 a5 dack0 dma acknowledge 0 16 ma c5 deot0 dma end of transfer 0 16 ma d5 dreq1 dma request 1 a4 dack1 dma acknowledge 1 16 ma b4 deot1 dma end of transfer 1 16 ma table 1. functional pin list (cont?d) bga signal description output drive table 2. lcd pin muxing pin assigned 4-bit mono stn single panel 8-bit mono stn single panel color stn single panel color stn dual panel 16-bit tft dd0 mustn3 mustn7 custn7 custn7 red0 dd1 mustn2 mustn6 custn6 custn6 red1 dd2 mustn1 mustn5 custn5 custn5 red2 dd3 mustn0 mustn4 custn4 custn4 red3 dd4 mustn3 custn3 custn3 red4 dd5 mustn2 custn2 custn2 green0 dd6 mustn1 custn1 custn1 green1 dd7 mustn0 custn0 custn0 green2 dd8 clstn7 green3 dd9 clstn6 green4 dd10 clstn5 blue0 dd11 clstn4 blue1 dd12 clstn3 blue2 dd13 clstn2 blue3 dd14 clstn1 blue4 dd15 clstn0 intensity
32-bit system-on-chip lh7a404 advance data sheet 11 table 3. detailed pin list bga signal reset state standby state pull up schmitt i/o slew rate output drive j9 vdd i/o ring power k9 m9 n9 p9 p11 p12 p13 p14 n14 m14 l14 k14 j14 j13 j11 j10 e4 vss i/o ring ground h4 l4 r4 w8 w11 w15 w19 t19 p19 m19 k19 g19 d18 d14 d10 d7 k3 vddc core power y5 y12 v20 n20 h20 d20 c12 c8 f3
lh7a404 32-bit system-on-chip 12 advance data sheet g2 vssc core ground m2 aa6 aa15 p21 k21 f21 b17 b10 b5 aa17 vdda1 analog power for pll1 ab17 vssa1 analog ground for pll1 aa18 vdda2 analog power for pll2 ab18 vssa2 analog ground for pll2 ab16 vdda3 analog power for tsc ab13 vssa3 analog ground for tsc a1 tdi input input yes i b1 tclk input input yes yes i b2 tdo low no change o 100 ma/ns 4 ma c1 tmst input no change yes i d3 npor input input yes i c2 nextpwr input input yes i c3 medchg input input yes i d1 batok input input yes i d2 nbatchg input input yes i e3 nureset input input yes i d4 wakeup input input yes i f4 uartcts2 input input i/o 110 ma/ns 8 ma e2 uartdcd2 input input i/o 110 ma/ns 8 ma e1 npwrfl input input yes i k10 uartdsr2 input input i/o 110 ma/ns 8 ma f2 uarttx1/uartirtx1 low no change i/o 110 ma/ns 8 ma f1 uartrx1/uartirrx1 input input i/o 110 ma/ns 8 ma g4 uarttxd2 low no change i/o 110 ma/ns 8 ma g3 uartrxd2 input input i/o 110 ma/ns 8 ma g1 kmidat input no change ext i/o 95 ma/ns 16 ma h3 kmiclk input no change ext i/o 95 ma/ns 16 ma table 3. detailed pin list (cont?d) bga signal reset state standby state pull up schmitt i/o slew rate output drive
32-bit system-on-chip lh7a404 advance data sheet 13 h2 col0 high high high i/o 100 ma/ns 8 ma h1 col1 j4 col2 j3 col3 j2 col4 j1 col5 k4 col6 k2 col7 l9 buz low low i/o 110 ma/ns 8 ma k1 sspclk low low i/o 110 ma/ns 8 ma l3 pgmclk low low i/o 110 ma/ns 8 ma l2 ssprx input low i/o 110 ma/ns 8 ma l1 ssptx input low i/o 110 ma/ns 8 ma m4 sspfrm high input i/o 110 ma/ns 8 ma m3 pa0/lcdvd16 input no change i/o 110 ma/ns 8 ma m1 pa1/lcdvd17 n4 pa2 gpio port a no change i/o 110 ma/ns 8 ma n3 pa3 n2 pa4 n1 pa5 p4 pa6 p3 pa7 p2 pb0/uartrxd1 input no change i/o 110 ma/ns 8 ma l10 pb1/uarttxd3 input low if uart3 enabled else no change i/o 110 ma/ns 8 ma l11 pb2/uartrxd3 input no change i/o 110 ma/ns 8 ma m10 pb3/uartcts3 input no change i/o 110 ma/ns 8 ma m11 pb4/uartdcd3 input no change i/o 110 ma/ns 8 ma n10 pb5/uartdsr3 input no change i/o 110 ma/ns 8 ma p1 pb6/bmiswib/bmismbio input input if smb enabled else no change r1 pb7/bmismbclk r2 pc0/txd1 low no change i/o 95 ma/ns 16 ma r3 pc1 low no change i/o 95 ma/ns 16 ma t1 pc2 t2 pc3 t3 pc4 t4 pc5 u1 pc6 u2 pc7 u3 lcdfp/lcdsps low low when not in hr-tft mode i/o 95 ma/ns 16 ma u4 lcdcls low no change i/o 95 ma/ns 16 ma v1 lcdlp/lcdhrlp low low when not in hr-tft mode i/o 95 ma/ns 16 ma v2 lcdspl low no change i/o 95 ma/ns 16 ma v3 lcdubl low no change i/o 95 ma/ns 16 ma table 3. detailed pin list (cont?d) bga signal reset state standby state pull up schmitt i/o slew rate output drive
lh7a404 32-bit system-on-chip 14 advance data sheet v4 lcdspr low no change i/o 95 ma/ns 16 ma w1 lcdlbr high no change i/o 95 ma/ns 16 ma w2 lcdmod high no change i/o 95 ma/ns 16 ma w3 lcdps high no change i/o 95 ma/ns 16 ma y1 lcdclpower low no change i/o 95 ma/ns 16 ma y2 lcdrev high no change i/o 95 ma/ns 16 ma w4 pg0/ncfoe low no change i/o 110 ma/ns 8 ma aa1 pg1/ncfwe aa2 pg2/ncfiord ab1 pg3/ncfiowr ab2 pg4/ncfreg aa3 pg5/ncfce1 ab3 pg6/ncfce2 y3 pg7/pcdir ab4 ph0/cfreseta input no change i/o 110 ma/ns 8 ma aa4 ph1/cfa8/cfa24/ cfresetb y4 ph2/ncfena ab5 ph3/cfa9/cfa25/ncfenb aa5 ph4/ncfwait/ncfwaita w5 ph5/cfa10/ncfwaitb ab6 ph6/ac97reset y6 ph7/ncfstaten w6 lcdclkin input no change i ab7 nble2 high high i/o 95 ma/ns 16 ma aa7 lcdvd0 low low i/o 95 ma/ns 16 ma y7 lcdvd1 w7 lcdvd2 ab8 lcdvd3 aa8 pe0/lcdvd4 input low if 8 bit lcd enabled else no change i/o 95 ma/ns 16 ma y8 nble1 high high i/o 95 ma/ns 16 ma p10 lcdm low low i/o 95 ma/ns 16 ma ab9 lcddclk low low i/o 95 ma/ns 16 ma aa9 pe1/lcdvd5 input low if 8 bit lcd enabled else no change i/o 95 ma/ns 16 ma y9 pe2/lcdvd6 w9 pe3/lcdvd7 ab10 pd0/lcdvd8 low low if dual panel lcd else no change i/o 95 ma/ns 16 ma aa10 pd1/lcdvd9 y10 pd2/lcdvd10 w10 pd3/lcdvd11 ab11 pd4/lcdvd12 aa11 pd5/lcdvd13 y11 pd6/lcdvd14 ab12 pd7/lcdvd15 table 3. detailed pin list (cont?d) bga signal reset state standby state pull up schmitt i/o slew rate output drive
32-bit system-on-chip lh7a404 advance data sheet 15 aa12 batcntl input no change i/o 95 ma/ns 16 ma n11 bootwidth0 input input yes i n12 bootwidth1 w12 lr_ym a/d inputs a/d inputs aa13 an1 y13 an6 w13 ll_yp ab14 an5 aa14 an2 y14 ur_xm w14 an4 ab15 an3 y15 ul_xp aa16 xtalin oscilator y16 xtalout w16 ntest0 input input yes i y17 ntest1 w17 usbdcp input input i y18 usbdp high high yes w18 usbdn low low ab19 usbhdp0 high high i/o aa19 usbhdn0 low low i/o ab20 usbhdp1 high high i/o aa20 usbhdn1 low low i/o y19 usbhpwr high high o 95 ma/ns 16 ma ab21 usbhovrcurr input no change i ab22 ncs0 high high i/o 95 ma/ns 16 ma aa21 xtal32in oscilator y20 xtal32out n13 ncs1 high high i/o 95 ma/ns 16 ma aa22 oscen low low i/o 110 ma/ns 8 ma y21 ncs2 high high i/o 95 ma/ns 16 ma w20 ncs3/nmmcsel high high i/o 95 ma/ns 16 ma y22 ncs6 high no change i/o 95 ma/ns 16 ma w21 ncs7 high no change i/o 95 ma/ns 16 ma m13 nwait asynchronous memory controller wait i/o 95 ma/ns table 3. detailed pin list (cont?d) bga signal reset state standby state pull up schmitt i/o slew rate output drive
lh7a404 32-bit system-on-chip 16 advance data sheet w22 d0 low low i/o 95 ma/ns 16 ma v21 d1 u22 d2 u20 d3 t22 d4 t20 d5 r21 d6 r19 d7 p20 d8 n21 d9 m22 d10 m20 d11 l21 d12 l19 d13 k20 d14 j21 d15 j19 d16 h21 d17 g22 d18 g20 d19 f20 d20 e22 d21 e20 d22 d22 d23 c22 d24 b22 d25 b21 d26 d19 d27 b20 d28 a20 d29 b19 d30 b18 d31 v22 a0 high high i/o 95 ma/ns 16 ma v19 a1 table 3. detailed pin list (cont?d) bga signal reset state standby state pull up schmitt i/o slew rate output drive
32-bit system-on-chip lh7a404 advance data sheet 17 u21 a2/sa0 low low 95 ma/ns 16 ma u19 a3/sa1 t21 a4/sa2 r22 a5/sa3 r20 a6/sa4 p22 a7/sa5 n22 a8/sa6 n19 a9/sa7 m21 a10/sa8 l22 a11/sa9 l20 a12/sa10 k22 a13/sa11 j22 a14/sa12 j20 a15/sa13 h22 a16/sbank0 h19 a17/sbank1 g21 a18 f22 a19 f19 a20 e21 a21 e19 a22 d21 a23 c21 a24 a18 a25 a17 a26 c17 a27 a22 nscs0 high high i/o 95 ma/ns 16 ma c20 nscs1 a21 nscs2 c19 nscs3 a19 nswe high high i/o 95 ma/ns 16 ma c18 ncas high high i/o 95 ma/ns 16 ma d17 nras high high i/o 95 ma/ns 16 ma a16 scken3 depends on medchg low i/o 95 ma/ns 16 ma b16 sclk low no change i/o 190 ma/ns 24 ma c16 scke12 high no change i/o 95 ma/ns 16 ma d16 scke0 high no change i/o 95 ma/ns 16 ma a15 nble3 high no change i/o 110 ma/ns 8 ma b15 nble0 high no change i/o 110 ma/ns 8 ma c15 dqm0 data mask for synchronous memories i/o 95 ma/ns 16 ma d15 dqm1 a14 dqm2 b14 dqm3 c14 noe high high i/o 95 ma/ns 16 ma a13 nwe0 high high i/o 95 ma/ns 16 ma table 3. detailed pin list (cont?d) bga signal reset state standby state pull up schmitt i/o slew rate output drive
lh7a404 32-bit system-on-chip 18 advance data sheet note: ?no change? means the pin remains as it was programmed prior to entering the standby state. b13 sciio input low i/o 95 ma/ns 16 ma c13 sciclk input low i/o 95 ma/ns 16 ma d13 scireset input low i/o 95 ma/ns 16 ma a12 scivccen low no change o 95 ma/ns 16 ma b12 pwmen0 high/low high/low i/o 110 ma/ns 8 ma d12 pwmen1 high/low high/low i/o 110 ma/ns 8 ma a11 pwm0 input no change i/o 110 ma/ns 8 ma b11 pwm1 input no change i/o 110 ma/ns 8 ma c11 pwm2 input no change i/o 110 ma/ns 8 ma d11 pwm3 input no change i/o 110 ma/ns 8 ma a10 pwmsync0 input no change i/o 110 ma/ns l13 pf0 input no change i/o 110 ma/ns 8 ma k13 pf1 l12 pf2 k12 pf3 j12 pf4 k11 pf5/scidetect c10 pf6 a9 pf7 b9 ac97clk input input i/o 110 ma/ns 8 ma c9 ac97out low low i/o 110 ma/ns 8 ma d9 ac97sync low low i/o 110 ma/ns 8 ma a8 ac97in input input i/o 110 ma/ns 8 ma b8 mmcclk/spiclk low low i/o 110 ma/ns 8 ma d8 mmccmd/spidi input input i/o 110 ma/ns 8 ma a7 mmcdata0/spido input input i/o 110 ma/ns 8 ma b7 mmcdata1 input input i/o 110 ma/ns 8 ma c7 mmcdata2 input input i/o 110 ma/ns 8 ma a6 mmcdata3 input input i/o 110 ma/ns 8 ma b6 ctclkin input no change i c6 nresetout low high o 95 ma/ns 16 ma d6 dreq0 input no change i a5 dack0 input no change i/o 95 ma/ns 16 ma c5 deot0 input no change i/o 95 ma/ns 16 ma d5 dreq1 input no change i a4 dack1 input no change i/o 95 ma/ns 16 ma b4 deot1 input no change i/o 95 ma/ns 16 ma c4 pe4 input input i/o 95 ma/ns 16 ma a3 pe5 b3 pe6 a2 pe7 table 3. detailed pin list (cont?d) bga signal reset state standby state pull up schmitt i/o slew rate output drive
32-bit system-on-chip lh7a404 advance data sheet 19 system descriptions arm922t processor the lh7a404 microcontroller features the arm922t cached core with an adv anced high-performance bus (ahb) interface. the processor is a member of the arm9t family of processors. for more information, see the arm document, ?arm922t technical reference manual?, available on arm? s website at www.arm.com. clock and state controller the clocking scheme in the lh7a404 is based around two primary oscillator inputs. these are the 14.7456 mhz input crystal and the 32.768 khz real time clock oscillator; see figure 3. the 14.7456 mhz oscil- lator supplies the main sys tem clock domains for the lh7a404. the 32.768 khz oscillator controls the power-down operations and real time clock peripheral. the clock and state controlle r provides the clock gating and frequency division necessary, and then supplies the clocks to the processor and rest of the system. the amount of clock gating that actually takes place depends on the power saving mode selected. the 32.768 khz clock provides the source for the real time clock tree and power-down logic. this clock is used for the power state control and is the only clock in the lh7a404 that runs continuously. the 32.768 khz clock is divided down to 1 hz for the real time clock counter using a ripple divider to save power. the 14.7456 mhz source is used to generate the main system clocks for the lh7a404. it is the source for pll1 and pll2, the primary clock for the peripher- als, and the source clock to the programmable clock (pgm) divider. pll1 provides the main clock tree for the chip. it gen- erates the following clocks: fclk, hclk, and pclk. fclk is the clock that drives the arm922t core. hclk is the main bus (ahb) clock, as such it clocks all memory interfaces, bus arbitrators and the ahb peripherals. hclk is generated by dividing fclk by 1, 2, 3, or 4. hclk can be gated by the system to enable low power operation. pclk is the peripheral bus (apb) clock. it is gener- ated by dividing hclk by either 2, 4, or 8. pll2 generates a fixed 48 mhz clock signal for the usb peripheral. figure 2. application diagram codec battery dc to dc voltage generation circuitry multimedia card touch screen contr. mmc/sd sci pcmcia compact flash usb host device host sdram sram rom flash dma ac97 stn/tft/ hr-tft ir gpio ssp uart lh7a404 pc card lh7a404-2 1 2 3 4 5 6 7 8 9 * 0 # bmi smart card
lh7a404 32-bit system-on-chip 20 advance data sheet power modes the lh7a404 has three operational states: run, halt, and standby. during run all clocks are hardware enabled and the processor is clocked. in the halt mode the device is functioning, but the processor clock is halted while it waits for an event such as a key press. standby equates to the computer being switched ?off?, i.e. no display (lcd disabl ed) and the main oscillator is shut down. reset modes three external signals can generate resets to the lh7a404: npor (power on reset), npwrfl (power failure) and nureset (user reset). if any of these are active, a system reset is internally generated. an npor reset performs a full system reset. the npwrfl and nureset resets perform a full system reset except for the sdram refresh control, sdram global configura- tion, sdram device configuration, and the rtc peripheral registers. the sdram controller issues a self-refresh command to external sdram before the system enters an npwrfl and nureset reset. this allows the system to mainta in its real time clock and sdram contents. at reset termination, the chip enters standby mode. once in the run mode the pwrsr reg- ister can be interrogated to determine the nature of the reset and the trigger source, after which software can then take appropriate actions. data paths the data paths in the lh7a404 are: the amba ahb bus the amba apb bus the external bus interface the lcd ahb bus the dma busses. amba ahb bus the advanced microprocessor bus architecture ahb (amba ahb) is a high speed 32-bit-wide data bus. the amba ahb is for high- performance, high-clock-fre- quency system modules. peripherals with high bandwidth requirements are connected to the lh7a404 core processor using the ahb bus, boot rom, vectored interrupt controllers, and usb device. these include the external and inter- nal memory interfaces, the lcd registers, palette ram and the bridge to the advanced peripheral bus (apb) interface. the apb bridge tr ansparently converts the ahb access into the slow er speed apb accesses. all control registers for the apb peripherals are pro- grammed using the ahb-to- apb bridge interface. the main ahb data and address lines are configured using a multiplexed bus. this removes the need for tri-state buffers and bus holders and simplifies bus arbitration. figure 3. clock and state controller block diagram 14.7456 mhz main osc. hclk 32.768 khz rtc osc. /2, /4, /8 pclks fclk hclk (to processor core) lh7a404-6 state controller divide register
32-bit system-on-chip lh7a404 advance data sheet 21 amba apb bus the amba apb bus is a low speed 32-bit-wide peripheral data bus. the speed of the apb bus is selected by dividing the clock speed of the ahb bus by two, four, or eight. external bus interface (ebi) the external bus interface (ebi) provides a 32-bit wide, high speed gateway to external memory devices. the supported memory devices include: asynchronous ram/rom/flash synchronous dram/flash pcmcia interfaces compact flash interfaces. the ebi can be controlled by either the asynchro- nous memory controller or synchronous memory con- troller. there is an arbiter on the ebi input, with priority given to the synchronous memory controller interface. lcd bus the lcd controller has its own local memory bus that connects it to the system?s embedded memory and external sdram. the function of this local data bus is to allow the lcd controller to perform its video refresh function without congesting the main ahb bus. this leads to better system performance and lower power consumption. there is an arbiter on both the embed- ded memory and the synchronous memory controller. in both cases the lcd bus is given priority. dma buses the lh7a404 has a dma system which connects the higher speed/higher dat a volume apb peripherals (mmc, usb and ac97) to the ahb bus. this enables the efficient transfer of data between these peripherals and external memory without the intervention of the arm922t core. the dma engine does not support memory-to-memory transfers. usb host controller dma bus the usb host controller has its own dma control- ler. it acts as another bus master on the ahb bus. it does not interact with the non-usb dma controller except in bus arbritration. memory map the lh7a404 system has a 32-bit-wide address bus, allowing addressing up to 4gb of memory. this mem- ory space is subdivided into a number of memory banks, shown in figure 4. four of these banks (each 256mb) are allocated to the synchronous memory controller. eight banks (each 256mb) are allocated to the asynchronous memory controller. two of these eight banks are designed for pcmcia systems. part of the remaining memory space is allocated to the embed- ded sram, and to the control registers of the ahb and apb. the rest of the memory space is not used. the lh7a404 can boot from either synchronous or asynchronous rom/flash. the selection is determined by the value of the medchg pin at power-on reset as shown in table 4. when booting from synchronous memory, bank 4 (nscs3) is mapped into memory loca- tion zero. when booting from asynchronous memory, memory bank 0 (nscs0) is mapped into memory loca- tion zero. figure 4 shows the memory map of the lh7a404 system for the two boot modes. once the lh7a404 has booted, the boot code can configure the arm922t mmu to remap the low mem- ory space to a location in ra m. this allows the user to set the interrupt vector table. table 4. boot modes boot modes latched boot- width1 latched boot- width0 latched medchg 8-bit rom 0 0 0 16-bit rom 0 1 0 32-bit rom 1 0 0 32-bit rom 1 1 0 16-bit sflash (initializes mode register) 0 0 1 16-bit srom (initializes mode register) 0 1 1 32-bit sflash (initializes mode register) 1 0 1 32-bit srom (initializes mode register) 1 1 1
lh7a404 32-bit system-on-chip 22 advance data sheet figure 4. memory mapping for each boot mode async. mem (ncs0) f000.0000 sync. mem (nsdce2) sync. mem (nsdce1) d000.0000 sync. mem (nsdce0) not used b001.4000 embedded sram not used 8000.3800 e000.0000 c000.0000 ahb internal registers apb internal registers 8000.0000 async. mem (ncs7) async. mem (ncs6) 6000.0000 pcmcia (slot1) pcmcia (slot0) 4000.0000 async. mem (ncs3) async. mem (ncs2) 2000.0000 7000.0000 5000.0000 b000.0000 8000.2000 3000.0000 1000.0000 async. mem (ncs1) sync. rom (nsdce3) 0000.0000 sync. memory boot sync. mem (nsdce3) sync. mem (nsdce2) sync. mem (nsdce1) sync. mem (nsdce0) not used embedded sram not used ahb internal registers apb internal registers async. mem (ncs7) async. mem (ncs6) pcmcia (slot1) pcmcia (slot0) async. mem (ncs3) async. mem (ncs2) async. mem (ncs1) async. rom (nsdce0) 256mb 256mb 256mb 256 mb 256mb 256mb 256mb 256mb 256mb 80kb 256mb 256mb 256mb async. memory boot lh7a404-7
32-bit system-on-chip lh7a404 advance data sheet 23 vectored interrupt controller (vic) the lh7a404 vic controls the interrupts of up to 32 different sources. two vics are daisy-chained together to support up to 64 different interrupts. the vic sup- ports both fiq and irq interrupts. fiq interrupts have a higher priority than irq interrupts. each vic can sup- port up to 16 vectored interrupts, for a total of 32 vec- tored interrupts. if two interrupts with the same priority become active at the same time, the priority must be resolved in software. wh en an interrupt becomes active, the vic generates an fiq or irq if the corre- sponding mask bit is set. no latching of interrupts takes place in the vic. after a power-on reset, all mask register bits are cleared, masking all interrupts. the mask bits must be set by software after power-on reset for any interrupts to be enabled. a vectored interrupt has improved latency as it pro- vides direct information about where its service routine is located and eliminates software arbitration needed with a simple interrupt controller. the vics continue to operate in halt and standby modes, so external interrupts may bring the chip out of these low power modes. external bus interface the arm922t, lcd controller, and dma engine have access to an extern al memory system. the lcd controller has access to an internal frame buffer in embedded sram and an extension buffer in synchro- nous memory for large displays. the processor and dma engine share the main system bus, providing access to all external memo ry devices and the embed- ded sram frame buffer. an arbitration unit ensures that control over the external bus interface (ebi) is only granted when an existing access has been completed. see figure 5. figure 5. external bus interface block diagram arm922t lcd controller embedded sram 80kb lcd ahb bus system ahb bus lcd mmu dma controller asynchronous memory controller bus arbiter synchronous memory controller external bus interface (ebi) arbiter sdram sram sdram rom data address/ control lh7a404-8
lh7a404 32-bit system-on-chip 24 advance data sheet embedded sram the lh7a404 incorporates 80kb of embedded sram. this embedded memory is used for storing code, data, or lcd frame data and is contiguous with external sdram. the 80kb is large enough to store a qvga panel (320 240) at 8 bits per pixel, equivalent to 70kb of information. locating the frame buffer on chip reduces the overall power consumed by any application that uses the lh7a404. normally, the system performs external accesses to acquire this data. the lcd controller auto- matically uses an overflow frame buffer in sdram if a larger screen size is required. this overflow buffer can be located on any 4kb page boundary in sdram, allowing software to set th e mmu (in the lcd control- ler) page tables such that the two memory areas appear contiguous. byte, half-word and word accesses are permissible. static memory controller (smc) the asynchronous static memory controller (smc) provides an interface between the amba ahb system bus and external (off-chip) memory devices. the smc simultaneously supports up to eight inde- pendently configurable memo ry banks. each memory bank can support: sram rom flash eprom burst rom memory. each memory bank may use devices using either 8-, 16-, or 32-bit external memory data paths. the memory controller can be configured to support either little- endian or big-endian operation. the memory banks can be configured to support: non-burst read and write accesses only to high- speed cmos static ram non-burst write accesses, nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory. the smc has six main functions: memory bank select access sequencing wait state generation byte lane write control external bus interface compact flash or pcmcia interfacing. sdram (synchronous) memory controller the sdram (synchronous) memory controller pro- vides a high speed memory interface to a wide variety of synchronous memory devices, including synchro- nous dram, synchronous flash and synchronous roms. the key features of the controller are: lcd dma port for high bandwidth up to four synchronous memory banks can be inde- pendently set up includes special configuration bits for synchronous rom operation includes ability to progr am synchronous flash devices using write and erase commands on booting from synchronous rom, (and optionally with synchronous flash), a configuration sequence is performed before releasing the processor from reset data is transferred between the controller and the synchronous dram in four-word bursts. longer transfers within the same page are concatenated, forming a seamless burst programmable for 16- or 32-bit data bus size two reset domains enable synchronous dram con- tents to be preserved over a ?soft? reset power saving synchronous memory scke and external clock modes provided. secure digital/mu ltimediacard (mmc) the sd memory card (secure digital memory card) is a flash-based memory card that meets the security, capacity, performance, and environment requirements inherent in electronic dev ices. the sd memory card host supports multimediacard (mmc) operation as well and is forward compatible. the main difference between sd card and mmc is the initialization process. the secure digital and mmc adapter can be used as an mmc card or as an sd card and supports the full mmc/sd bus protocol as defined in the mmc system specification 2.11 provided by the mmc definition group and the sd memory card spec v1.0 from the sd group. the controller can also implement the spi inter- face to the cards. sd/mmc interface description the sd/mmc controller uses the three-wire serial data bus (clock, command, and data) to input and out- put data to and from the mmc card, and to configure and acquire status information from the card?s regis- ters. the sd differs only in that it has four data lines.
32-bit system-on-chip lh7a404 advance data sheet 25 the sd/mmc bus lines can be divided into three groups: power supply: vss1, vss2 and vdd data transfer: mmccmd , mmcdat0, mmcdat1, mmcdat2, mmcdat3 (for mmc, do not use mmcdat1, mmcdat2, mmcdat3) clock: mmcclk mmc bus lines can be divided into three groups: power supply: vdd and vss data transfer: mmccmd, mmcdata clock: mmclk. mmc adapter the mmc adapter implements mmc specific func- tions, serves as the bus master for the mmc bus and implements the standard interface to the mmc cards (card initialization, crc generation and validation, command/response transactions, etc.). smart card interface (sci) the sci (iso7816) connects to an external smart card reader. the sci can autonomously control data transfer to and from the smart card. transmit and receive data fifos are provided to reduce the required interaction between the cpu core and the peripheral. sci features supports asynchronous t0 and t1 transmission pro- tocols supports clock rate conversion factor f = 372, with bit rate adjustment factors d = 1, 2, or 4 supported eight-character-deep buffered tx and rx paths direct interrupts for tx a nd rx fifo level monitoring interrupt status register hardware-initiated card deactivation sequence on detection of card removal software-initiated card deactivation sequence on transaction complete limited support for synchronous smart cards via reg- istered input/output. programmable parameters smart card clock frequency communication baud rate protocol convention card activation/deactivation time check for maximum time for first character of answer to reset (atr) reception check for maximum duration of atr character stream check for maximum time of receipt of first character of data stream check for maximum time allowed between characters character guard time block guard time transmit/receive character retry. direct memory access controller (dma) the dma controller can be used to interface streams from 20 internal peripherals to the system memory using 10 fully-independent programmable channels which consist of fi ve m2p (transmit) channels and five p2m (receive) channels. the following peripherals may be allocated to the 10 channels: usb device usb host sd/mmc aac uart1 uart2 uart3 each of the above peripherals contain one tx and one rx channel, except the aac, which contains three tx and rx channels. these pe ripherals also have their own bi-directional dma bus, capable of simultaneously transferring data in both directions. all memory trans- fers take place via the main system ahb bus. the dma controller can also be used to interface streams from memory-to-memory (m2m) or memory- to-external peripheral (m2p) using two dedicated m2m channels. external handshak e signals are available to suport memory-to-/from-external peripheral (m2p/ p2m) transfers. a software trigger is available for m2m transfers only.
lh7a404 32-bit system-on-chip 26 advance data sheet the dma features: two dedicated channels for m2m and external m2p/ p2m ten fully independent, programmable dma control- ler internal m2p/p2m channels (5 tx and 5 rx) channels assignable to one of a number of different peripherals independent source and destination address regis- ters. source and destination can be programmed to auto-increment or not auto-increment for m2m chan- nels two buffer descriptors per m2p and m2m channel to avoid potential data under/over-flow due to software introduced latency. a buffer refers to the area in sys- tem memory that is characterized by a buffer descriptor, ie., a start address and the length of the buffer in bytes no amba wrapping bursts for dma channels; only incrementing bursts are supported buffer size independent of the peripheral?s packet size for the internal m2p channels. transfers can automatically switch between buffers maskable interrupt generation internal arbitration between dma channels, plus support for an ahb bus arbiter dma data transfer sizes, byte, word and quad-word data transfers are supported using a 16-byte data bay. maximum data transfer size per m2m channel is programmable per-channel clock gating reducing power in chan- nels that have not been enabled by software. see the ?clock and state co ntroller? section. a set of control and status registers are available to the system processor for se tting up dma operations and monitoring their status. system interrupts are gen- erated when any/all of the dma channels wish to inform the processor to update the buffer descriptor. the dma controller can service 10 out of 20 possible peripherals using the ten dma channels, each with its own peripheral dma bus capable of simultaneously transferring data in both directions. the sd/mmc, uart1/2/3, usb device, and usb host peripherals can each use two dma channels, one for transmit and one for receive. the aac peripheral can use six dma channels (three transmit and three receive) to allow different sample frequency data queues to be handled with low software overheads. the dma controller includes an m2m transfer fea- ture allowing block moves of data from one memory address space to another with minimum of program effort and time. an m2m software trigger capability is provided. the dma controlle r can also fill a block of memory with data from a single location. the dma controller?s m2m channels can also be used in m2p/p2m mode. a set of external handshake signals, dreq, dack and tc/deot are provided for each of two m2m channels. dreq (input) can be programmed edge or level active, and active high or low. the peripheral may hold dreq active for the duration of the block transfers or may assert/deassert on each transfer. dack (output) can be programmed active high or low. dack will assert and return to de- asserted with each read or write, the timing coinciding with noe or nwe from the ebi. tc/deot is a bidirectional signal with programma- ble direction and active polarity. when configured as an output, the dma will assert te rminal count (tc) on the final transfer to coincide with the dack, typically when the byte count has expired. when configured as an input, the peripheral must assert deot concurrent with dreq for the final transfer in the block. transfer is terminated when deot is asserted by the external peripheral or when the byte count expires, whichever occurs first. status bits indicate if the actual byte count is equal to the programmed limit, and if the count was terminated by per ipheral asserting deot. terminating the transfer causes a dma interrupt on that channel and rollover to the ?other? buffer if so con- figured. for byte- or word-wide peripherals, the dma is pro- grammed to request byte- or word-wide ahb transfers respectively. the dma does not issue an ahb hreq for a transfer until it has dreq asserted after a dack for the previous transfer; and the previous transfer has been asserted for the duration of the programmed wait states in the smc (and possibly dreq is sampled in the cycle dack is deasserted). usb device the features of the usb are: fully compliant to usb 1.1 specification provides a high-level interface that shields the firm- ware from usb protocol details compatible with both openhci and intel uhci standards supports full-speed (12 mbps) functions supports suspend and resume signalling.
32-bit system-on-chip lh7a404 advance data sheet 27 usb host controller the features of the usb host controller are: open host controller inte rface specification (open- hci) rev. 1.0 compatible universal serial bus specification rev. 1.1 compatible support for both low speed and high speed usb devices root hub has two downstream ports dma functionality. color lcd controller the lh7a404?s lcd controller is programmable to support up to 1,024 768, 16-bit color lcd panels. it interfaces directly to st n, color stn, tft, and hr-tft panels. unlike other lcd controllers, the lh7a404?s lcd controller incorporates the timing conversion logic from tft to hr-tft, allowing a direct interface to hr- tft and minimizing ex ternal chip count. the color lcd controller features support for: up to 1,024 768 resolution 16-bit video bus stn, color stn, hr-tft, tft panels single and dual scan stn panels up to 15 gray shades up to 64 k-colors advanced audio codec (aac) the advanced audio codec controller (ac97) includes a 5-pin serial interface to an external audio codec. the aac link is a bi-d irectional, fixed rate, serial pulse code modulation (pcm) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. the aac controller contains logic that controls the aac link to the audio codec and an interface to the amba apb. its main features include: serial-to-parallel conversion for data received from the external codec parallel-to-serial conversion for data transmitted to the external codec reception/transmission of control and status infor- mation via the amba apb interface support for up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. the transmit and receive paths are buffered with internal fifo memories, allowing data to be stored indepen- dently in both transmit and receive modes. the out- going data for the fifos can be written via either the apb interface or wit h dma channels 1-3. audio codec interface (aci) the aci provides: a digital serial interface to an off-chip 8-bit codec all the necessary clocks and timing pulses to per- form serialization or de-serialization of the data stream to or from the codec device. the interface supports full duplex operation and the transmit and receive paths are buffered with internal fifo memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. the aci includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip aci clock input (aciclk). transmit data values are output synchronous with the rising edge of the bit clock output. receive data values are sampled on the falling ed ge of the bit clock output. the start of a data frame is indicated by a synchroniza- tion output signal that is coincident with the bit clock. pulse width modulator (pwm) the pulse width modulator features: configurable dual output separate input clocks for each pwm output 16-bit resolution programmable synchronous mode support ? allows external input to start pwm programmable pulse width (duty cycle), interval (fre- quency), and polarity ? static programming: when the pwm is stopped ? dynamic programming: when the pwm is running ? updates duty cycle, frequency, and polarity at end of a pwm cycle the pwm is a configurable dual-output, dual-clock- input amba slave module, and connects to the apb.
lh7a404 32-bit system-on-chip 28 advance data sheet synchronous serial port (ssp) the ssp is a master-only interface for synchro- nous serial communication with peripheral devices that have either motorola spi, national semicon- ductor microwire, or texas instruments synchronous serial interfaces. the ssp performs serial-t o-parallel conversion on data received from a peripheral device. the transmit and receive paths are buffered with internal fifo mem- ories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. serial data is transmitted on ssptxd and received on ssprxd. the lh7a404 ssp includes a programmable bit rate clock divider and prescaler to generate the serial output clock sclk from the input clock sspclk. bit rates are supported to 2 mhz and beyond, subject to choice of frequency for sspclk; the maximum bit rate will usu- ally be determined by per ipheral device?s capability. uart/irda the lh7a404 contains three uarts; uart1, uart2, and uart3. the uart performs: serial-to-parallel conversion on data received from the peripheral device parallel-to-serial conversion on data transmitted to the peripheral device. the transmit and receive paths can both be routed through the dma separately or simultaneously, and are buffered with internal fifo memories. this allows up to 16 bytes to be stored independently in both transmit and receive modes. the uart can generate: four individually maskable interrupts from the receive, transmit and modem status logic blocks a single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. if a framing, parity or break error occurs during reception, the appropriate error bit is set and stored in the fifo. if an overrun condition occurs, the overrun register bit is set immediately and the fifo data is pre- vented from being overwritten. uart1 also supports irda 1.0 (15.2 kbit/s). the modem status input signals clear to send (cts), data carrier detect (dcd) and data set ready (dsr) are supported on uart2 and uart3. timers the lh7a404 includes three programmable timers. each of the timers can operate in two modes: free run- ning and pre-scale. the timers are programmed using four registers; load, value, control, and clear. two identical timers, timer 1 (tc1) and timer 2 (tc2), use clock sources of either 508 khz or 2 khz. the clock source and mode is selectable by writing to the appropriate bits in the system control register. each timer has a 16-bit read/write data register and a control register. the timer is loaded with the value written to the data register immediately. this value is then decre- mented on the next active clock edge to arrive after the write. when the timer underflows, it immediately asserts its appropriate interrupt. timer 3 (tc3) has the same basic operation, but is clocked from a single 7.3728 mhz source. once the timer has been enabled and written to, it decrements on the next rising edge of the 7.3728 mhz clock after the data register has been updated. free-running mode in free-running mode, the timer wraps around to 0xffff when it underflows and continues counting down. pre-scale mode in pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. this mode can be used to produce a pro- grammable frequency to drive the buzzer or generate a periodic interrupt. real time clock (rtc) the rtc provides a basic alarm function or long time-base counter. this is achieved by generating an interrupt signal after counting for a programmed num- ber of cycles of a real-time clock input. counting in one second intervals is achieved by use of a 1 hz clock input to the rtc.
32-bit system-on-chip lh7a404 advance data sheet 29 keyboard and mouse interface (kmi) the keyboard and mouse interface has the follow- ing features: ibm ps2 or at-compatible keyboard or mouse inter- face half-duplex bidirectional synchronous serial inter- face using open-drain outputs for clock and data. programmable 4-bit reference clock divider polled or interrupt-driven mode separately maskable transmit and receive interrupts single combined interrupt output odd parity generation and checking register bits for override of keyboard clock and data lines. additional test registers and modes are implemented for functional verification and manufacturing test. touch screen controller (tsc) the touch screen controller is a complete interface to a touch screen as used in portable personal devices. it combines the front-end bi asing and control circuitry with analog-to-digital conversion, reference genera- tion, and digital control and interface functions to com- pletely replace external ics used to implement this interface. the features are: 10-bit a/d converter with integrated sample-and- hold, fully differential, high impedance signal and ref- erence inputs. input active matrix for bias and control circuits nec- essary for connection to external 4- and 5-wire touch sensitive panels. auxiliary functions such as temperature sense, pen pressure sense, battery voltage sense, in addition to normal direct voltage inputs. a 10-channel multiplexer for routing user-selected inputs to a/d 16 16 fifo for 10-bit digital output of a/d pen down sensor to generate interrupts to the host low power circuitry and power control modes to min- imize in-system po wer dissapation. conversion automation to maximize flexibility while minimizing cpu management and interrupt overhead supply voltage 3.0 v - 3.6 v configurable input pads so that when an analog input is not being used, the pad can be used as a gpio. battery monitor interface (bmi) the bmi is a serial communication interface speci- fied for two types of battery monitors/gas gauges. the first type employs a single wire interface. the second interface employs a two-wire multi-master bus, the smart battery system specification. if both interfaces are enabled at the same time, the single wire interface will have priority. single wire interface the single wire interface performs: serial-to-parallel conversion on data received from the peripheral device parallel-to-serial conversion on data transmitted to the peripheral device data packet coding/decoding on data transfers (incorporating start/data/stop data packets) the single wire interface uses a command-based protocol in which the host initiates a data transfer by sending a writedata/command word to the battery monitor. this word always contains the command sec- tion, which tells the single wire interface device the location for the current transaction. the most signifi- cant bit of the command determines if the transaction is read or write. in the case of a write transaction the word will also contain a writ edata section with the data to be written to the peripheral. smart battery interface the smart battery interface performs: serial-to-parallel conversion on data received from the peripheral device parallel-to-serial conversion of data transmitted to the peripheral device. the smart battery interface uses a two-wire multi- master bus (the smbus), allowing multiple bus masters to be connected to it. a master device initiates a bus transfer and provides the cl ock signals. a slave device can receive data provided by the master or it can provide data to the master. since more than one device may attempt to take control of the bus as a master, smbus provides an arbitration me chanism by relying on the wired-and connection of all smbus interfac es to the smbus.
lh7a404 32-bit system-on-chip 30 advance data sheet dc-to-dc converter the features of the dc-dc converter interface are: dual drive pwm outputs with independent closed loop feedback software programmable configuration of one of 8 output frequencies (each being a fixed division of the input clock). software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. hardware-configured output polarity (for positive or negative voltage generation) during power-on reset via the polarity select inputs dynamically switched pwm outputs to one of a pair of preprogrammed frequency/duty cycle combina- tions via external pins. watchdog timer (wdt) the watchdog timer provides hardware protection against malfunctions. it is a programmable timer that is reset by software at regular intervals. failure to reset the timer will cause an fiq in terrupt. failure to service the fiq interrupt generates a system reset. features of the wdt: timing derived from the system clock 16 programmable time-out periods: 2 16 through 2 31 clock cycles generates a system reset (resets lh7a404) or a fiq interrupt whenever a time-out period is reached software enable, lockout, and counter-reset mecha- nisms add security against inadvertent writes protection mechanism guards against interrupt-ser- vice-failure: ? the first wdt time-out triggers fiq and asserts nwdfiq status flag ? if fiq service routine fails to clear nwdfiq, then the next wdt time-out tr iggers a system reset. general purpose i/o (gpio) the gpio has eight ports, each with a data register and a data direction register. it also has added regis- ters including keyboard scan, pinmux, gpio inter- rupt enable, intype1/2, gpiofeoi and pghcon. the data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the gpio pins. the gpio interrupt enab le, intype1/2, and the gpiofeoi registers control edge-triggered interrupts on port f. the pinmux register controls which signals are from port d and port e when they are set as out- puts, while the pghcon controls the operations of port g and port h.
32-bit system-on-chip lh7a404 advance data sheet 31 electrical specifications absolute maximum ratings note: these stress ratings are only fo r transient conditions. oper- ation at or beyond absolute ma ximum rating conditions may affect reliability and cause permanent damage to the device. recommended operat ing conditions notes: 1. core voltage should never exceed i/o voltage. 2. using 14.756 mhz main osci llator crystal and 32.768 khz rtc oscillator crystal. 3. commercial temperature range. 4. vddc = 1.62 v to 1.98 v. 5. vdd = 3.0 v to 3.6 v. 6. with clock frequency reduction. the lh7a404 has not ye t been characterized for the industrial temperature range. 7. using the lh7a404 below vdd = 3.0 v will affect the ac timing and the usb will not function. ac timing for vdd less than 3.0 v has not yet been characterized. parameter minimum maximum dc core supply voltage (vddc) - 0.3 v 2.4 v dc i/o supply voltage (vdd) - 0.3 v 4.6 v dc analog supply voltage (vdda1, vdda2) - 0.3 v 2.4 v dc analog supply voltage (vdda3) - 0.3 v 4.6 v storage temperature -55c 125c parameter minimum typical maximum notes dc core supply voltage (vddc) 1.62 v 1.8 v 1.98 v 1 dc i/o supply voltage (vdd) 1.62 v 3.3 v 3.6 v 7 dc analog supply voltage (vdda1, vdda2) 1.62 v 1.8 v 1.98 v dc analog supply voltage (vdda3) 3.0 v 3.3 v 3.6 v clock frequency 10 mhz 200 mhz 2, 3, 4, 5 commercial operating temperature 0c 25c +70c industrial operating temperature -40c 25c +85c 6
lh7a404 32-bit system-on-chip 32 advance data sheet dc/ac specificat ions (commercial) unless otherwise noted, all data provided under commercial dc/ac specifications are based on 0c to +70c, vddc = 1.62 v to 1.98 v, vdd = 3.3 v to 3.6 v, vdda1 and vdda2 = 1.62 v to 1.98 v; vdda3 = 3.0 to 3.6 v. dc specifications notes: 1. output drive 5 can sink 24 ma of current, but sources 16 ma of current. 2. both oscillators runn ing, lcd active; all ot her peripheral s stopped. 3. 32 khz oscillator running; all other peripherals stopped. 4. current consumption until oscillators are stabilized. ac test conditions symbol parameter min. max. unit conditions notes vih cmos and schmitt trigger input high voltage 2.0 v vil cmos and schmitt trigger input low voltage 0.8 v vhst schmitt trigger hyst eresis 0.35 v vil to vih voh cmos output high voltage, ou tput drive 1 2.6 3.6 v ioh = 2 ma output drive 2 2.6 3.6 v ioh = 4 ma output drive 3 2.6 3.6 v ioh = 8 ma output drive 4 and 5 2.6 3.6 v ioh = 16 ma 1 vol cmos output low voltage, output drive 1 0.0 0.4 v iol = 2 ma output drive 2 0.0 0.4 v iol = 4 ma output drive 3 0.0 0.4 v iol = 8 ma output drive 4 0.0 0.4 v iol = 16 ma output drive 5 0.0 0.4 v iol = 24 ma 1 iin input leakage current -10 10 a vin = vdd or gnd ioz output tri-state leakage current -10 10 a vout = vdd or gnd iactive active current (operating current) 180 ma ihalt halt current 6.0 ma 2 istandby standby current 20 a3 istartup startup current 50 a4 cin input capacitance 4 pf cout output capacitance 4 pf parameter rating unit dc i/o supply voltage (vdd) 3.0 to 3.6 v dc core supply voltage (vddc) 1.62 to 1.98 v input pulse levels vss to 3 v input rise and fall times 2 ns input and output timing reference levels vdd/2 v
32-bit system-on-chip lh7a404 advance data sheet 33 ac specifications (commercial) all signals described in table 5 relate to transi- tions following a reference clock signal. the illustra- tion in figure 6 represents all cases of these sets of measurement parameters. the reference clock signals in this design are: hclk, the system bus internal clock pclk, the peripheral bus clock sspclk, the synchronous serial port clock uartclk, the uart interface clock lcddclk, the lcd data clock from the lcd controller ac97clk, the ac97 clock sclk, the synchronous memory clock. all signal transitions are measured from the 50% point of the clock to the 50% point of the signal. for outputs from the lh7a404, tovxxx (e.g. tova) represents the amount of time for the output to become valid from the rising edge of the reference clock signal. maximum requirements for tovxxx are shown in table 5. the signal tohxxx (e.g. toha) represents the amount of time t he output will be held valid following the rising edge of the reference clock signal. minimum requirements for tohxxx are listed in table 5. for inputs, tisxxx (e.g. tisd) represents the amount of time the input signal must be valid before the rising edge of the clock signal. minimum requirements for tisxxx are shown in table 5. the signal tihxxx (e.g. tihd) represents the amount of time the output must be held valid following the rising edge of the reference clock signal. minimum requirements are shown in table 5. figure 6. lh7a404 signal timing table 5. ac signal characteristics signal type load drive symbol min. max. description asynchronous memory interface signals a[27:0] output 50 pf 8 ma tova 8 ns address valid toha 0 ns address hold d[31:0] output 50 pf 8 ma tovd 6 ns data valid tohd 2 ns data hold input tisd 2 ns data setup tihd 0 ns data hold ncs[7:0] output 30 pf 8 ma tovcs 8 ns chip select valid tohcs 0 ns chip select hold nwe[3:0] output 30 pf 8 ma tovwe 8 ns write enable valid tohwe 0 ns write enable hold nble[3:0] output 30 pf 8 ma tovble 8 ns byte lane enable valid tohble 0 ns byte lane enable hold noe output 30 pf 8 ma tovoe 8 ns ouput enable valid tohoe 0 ns ouput enable hold reference clock output signal (o) input signal (i) tovxxx tohxxx tisxxx tihxxx lh7a404-9
lh7a404 32-bit system-on-chip 34 advance data sheet notes: 1. tbd = to be determined, awaiting characterization. 2. for output drive strength specificat ions, refer to ? dc specifications?. synchronous memory interface signals a[15:2]/sa[13:0] output 50 pf 8 ma tova 8 ns address valid a[17:16]/sbank[1:0] output 50 pf 8 ma tovb 8 ns address valid/bank select valid d[31:0] output 50 pf 8 ma tovd 2 ns 6 ns data valid input tisd 4 ns data setup tihd 0 ns data hold ncas output 30 pf 8 ma tovca 2 ns 6 ns cas valid tohca 0 ns cas hold nras output 30 pf 8 ma tovra 2 ns 6 ns ras valid tohra 0 ns ras hold nswe output 30 pf 8 ma tovsdw 2 ns 6 ns write enable valid tohsdw 0 ns write enable hold scke[1:0] output 30 pf 8 ma tovc0 2 ns 6 ns clock enable valid dqm[3:0] output 30 pf 8 ma tovdq 2 ns 6 ns data mask valid nscs[3:0] output 30 pf 8 ma tovsc 2 ns 6 ns synchronous chip select valid tovhsc 0 ns synchronous chip select hold pc card (pcmcia) interface signals a[25:0] output 50 pf 8 ma tova 8 ns address valid ncfreg output 30 pf 8 ma tovdreg 2 ns 8 ns nreg valid tohdreg 0 ns nreg hold d[31:0] input tisd 4 ns data setup time tihd 0 ns data hold time ncfce1 output 30 pf 8 ma tovce1 0 ns 8 ns chip enable 1 valid tohce1 0 ns chip enable 1 hold ncfce2 output 30 pf 8 ma tovce2 0 ns 8 ns chip enable 2 valid tohce2 0 ns chip enable 2 hold ncfoe output 30 pf 8 ma tovoe 0 ns 8 ns output enable valid tohoe 0 ns output enable hold ncfwe output 30 pf 8 ma tovwe 0 ns 8 ns write enable valid tohwe 0 ns write enable hold mmc interface signals mmccmd output 100 pf 8 ma tovcmd tbd mmc command valid tohcmd tbd mmc command hold mmcdata output 100 pf 8 ma tovdat tbd mmc data valid tohdat tbd mmc data hold mmcdata input tisdat tbd mmc data setup tihdat tbd mmc data hold mmccmd input tovcmd tbd mmc command setup tihcmd tbd mmc command hold ac97 interface signals ac97out output 30 pf 8 ma tovac97 tbd ac97 output valid tohac97 tbd ac97 output hold ac97in input tisac97 tbd ac97 input setup tihac97 tbd ac97 input hold synchronous serial port (ssp) sspfrm input tissspfrm 14 ns sspfrm input valid ssptx output 50 pf 2 ma tovsspout tbd ssp transmit valid ssprx input tissspin 14 ns ssp receive setup table 5. ac signal characteristics (cont?d) signal type load drive symbol min. max. description
32-bit system-on-chip lh7a404 advance data sheet 35 asynchronous memory controller waveforms figure 7 shows the waveform and timing for an external asynchronous memory write. figure 8 shows the waveform and timing for an external asynchronous memory read, with one wait state. figure 9 shows the waveform and timing for an external asynchronous memory read, with two wait states. figure 7. external asynchronous memory write figure 8. external asynchronous memory read, one wait state hclk address data a[27:0] (note 1) d[31:0] ncs(x) nble[3:0], nwe t ova t ovd t ovd t ohd t ohcs t ohble , tohwe t oha t ovcs t ovble , t ovwe lh7a404-10 notes: 1. a[24:0] when sci used. 2. all signal transitions are measured from the 50% point of the clock to the 50% point of the signal. lh7a404-11 hclk address data a[25:0] d[31:0] ncsx noe tovoe tovcs tisd toha tihd tohcs tohoe tova 1 wait state data read note: all signal transitions are measured from the 50% point of the clock to the 50% point of the signal.
lh7a404 32-bit system-on-chip 36 advance data sheet figure 9. external asynchronous memory read, two wait states lh7a404-12 hclk address data a[25:0] d[31:0] ncsx noe t oha t ohoe t ohcs t ihd t isd 2 wait states data read tovoe tovcs tova note: all signal transitions are measured from the 50% point of the clock to the 50% point of the signal.
32-bit system-on-chip lh7a404 advance data sheet 37 synchronous memory controller waveforms figure 10 shows the waveform and timing for a syn- chronous burst read (page already open). figure 11 shows the waveform and timing for synchronous mem- ory to activate a bank and write. figure 10. synchronous burst read figure 11. synchronous bank activate and write t sclk lh7a404-13 sa[13:0], sbank[1:0] d[31:0] notes: 1. sdramcmd is the combination of nras, ncas, nsdwe, and nsdcsx. 2. tovxxx represents tovra, tovca, tovsdw, or tovsc. 3. tohxxx represents tohra, tohca, tohsdw, or tohsc. 4. ndqm is static low. 5. sdcke is static high. sclk sdramcmd t ovxxx t ovb t ohxxx read bank, column tova tisd tihd data n data n + 1 data n + 2 data n + 3 lh7a404-14 d[31:0] sclk sdcke sdramcmd tsclk tovc0 tovxxx tova tohxxx tova notes: 1. sdramcmd is the combination of nras, ncas, nsdwe, and nsdcsx. 2. tovxxx represents tovra, tovca, tovsdw, or tovsc. refer to the ac timing table. 3. tohxxx represents tohra, tohca, tohsdw, or tohsc. 4. ndqm is static low. active write data bank, row bank, column tovd tohd sa[13:0], sbank[1:0]
lh7a404 32-bit system-on-chip 38 advance data sheet ssp waveforms the synchronous serial po rt (ssp) supports three data frame formats: texas instruments? synchronous serial motorola spi national semiconductor microwire each frame format is between 4 and 16 bits in length, depending upon the programmed data size. each data frame is transmitted beginning with the most significant bit (msb) i.e. ?b ig endian?. for all three for- mats, the ssp serial clock is held low (inactive) while the ssp is idle. the ssp serial clock transitions only during active transmissio n of data. the sspfrm sig- nal marks the beginning and end of a frame. the sspen signal controls an off-chip line driver?s output enable pin. figure 12 and figure 13 show texas instruments synchronous serial frame format, figure 14 through figure 21 show the motorola spi format, and figure 22 and figure 23 show national conductor?s micro- wire data frame format. for texas instruments? synchronous serial frame for- mat, the sspfrm pin is pulsed prior to each frame?s transmission for one serial cl ock period beginning at its rising edge. for this frame format, both the ssp and the external slave device drive their output data on the ris- ing edge of the clock and latch data from the other device on the falling edge. see figure 12 and figure 13. figure 12. texas instruments synchronous serial frame format (single transfer) figure 13. texas instruments synchronous serial frame format (continuous transfer) lh7a404-24 sspclk sspfrm msb lsb ssptxd/ ssprxd 4 to 16 bits lh7a404-25 sspclk sspfrm ssptxd/ ssprxd msb lsb 4 to 16 bits
32-bit system-on-chip lh7a404 advance data sheet 39 for motorola spi format, the serial frame pin (ssp- frm) is active low. the spo and sph bits in ssp control register 0 determine sspclk and sspfrm operation in single and continuous modes. see figures 14 through 21. figure 14. motorola spi frame format (single transfer) with spo = 0 and sph = 0 figure 15. motorola spi frame format (continuous transfer) with spo = 0 and sph = 0 figure 16. motorola spi frame format (single transfer) with spo = 0 and sph = 1 lh7a404-26 sspclk nsspfrm ssprxd msb ssptxd 4 to 16 bits msb lsb lsb q note: q is undefined. lh7a404-27 sspclk nsspfrm ssptxd/ sssrxd 4 to 16 bits lsb lsb msb msb lh7a404-28 sspclk nsspfrm ssprxd ssptxd note: q is undefined. 4 to 16 bits lsb lsb q q msb msb
lh7a404 32-bit system-on-chip 40 advance data sheet figure 17. motorola spi frame format (continuous transfer) with spo = 0 and sph = 1 figure 18. motorola spi frame format (continuous transfer) with spo = 1 and sph = 1 figure 19. motorola spi frame format (single transfer) with spo = 1 and sph = 0 lh7a404-29 sspclk nsspfrm ssptxd/ sssrxd 4 to 16 bits lsb msb lsb msb lh7a404-30 sspclk nsspfrm ssptxd/ sssrxd 4 to 16 bits lsb msb lsb msb lh7a404-31 sspclk nsspfrm ssprxd ssptxd note: q is undefined. msb msb lsb lsb q 4 to 16 bits
32-bit system-on-chip lh7a404 advance data sheet 41 figure 20. motorola spi frame format (continuous transfer) with spo = 1 and sph = 0 figure 21. motorola spi frame format (single transfer) with spo = 1 and sph = 1 lh7a404-32 sspclk nsspfrm ssptxd/ ssprxd msb lsb msb lsb 4 to 16 bits lh7a404-33 sspclk nsspfrm ssprxd ssptxd 4 to 16 bits msb msb q lsb lsb q note: q is undefined.
lh7a404 32-bit system-on-chip 42 advance data sheet for national semiconductor microwire format, the serial frame pin (sspfrm) is active low. both the ssp and external sl ave device drive their output data on the falling edge of the cloc k, and latch data from the other device on the rising edge of the clock. unlike the full-duplex transmission of the other two frame formats, the national semiconducto r microwire format uti- lizes a master-slave messaging technique that oper- ates in half-duplex. when a frame begins in this mode, an 8-bit control message is transmitted to the off-chip slave. during this transmission no incoming data is received by the ssp. after the message ha s been sent, the external slave device decodes the message. after waiting one serial clock period after the last bit of the 8- bit control message was received it responds by return- ing the requested data. the returned data can be 4 to 16 bits in length, making the total frame length between 13 to 25 bits. see figure 22 and figure 23. figure 22. microwire frame format (single transfer) figure 23. microwire frame format (continuous transfers) lh7a404-34 lsb msb 0 lsb msb 8-bit control sspclk nsspfrm ssptxd ssprxd 4 to 16 bits output data lh7a404-35 sspclk nsspfrm ssptxd ssprxd 4 to 16 bits output data 8-bit control msb msb lsb lsb 0 lsb msb
32-bit system-on-chip lh7a404 advance data sheet 43 pc card (pcmcia) waveforms figure 24 shows the waveforms and timing for a pcmcia attribute memory read transfer, figure 25 shows the waveforms and timing for a pcmcia attribute memory write transfer, figure 26 shows the waveforms and timing for a pcmcia common memory read trans- fer, and figure 27 shows the waveforms and timing for a pcmcia common memory write transfer. figure 24. pcmcia attribute memory read transfer tova toha tovdreg hclk a[25:0] ncfreg ncfce1 ncfce2 ncfoe ncfwe d[31:0] tovce1 tohdreg tohce1 tovoe tohoe tihd tisd d[7:0] (even byte) lh7a404-15
lh7a404 32-bit system-on-chip 44 advance data sheet figure 25. pcmcia attribute memory write transfer hclk a[25:0] d[7:0] (even byte) tova toha tovce1 tohce1 tovwe tohwe tihd tisd lh7a404-16 ncfreg ncfce1 ncfce2 ncfoe ncfwe d[31:0]
32-bit system-on-chip lh7a404 advance data sheet 45 figure 26. pcmcia common memory read transfer tova toha tovce1 hclk a[25:0] tovce2 tohce1 tohce2 tovoe tohoe tihd tisd d[15:0] (word) lh7a404-17 ncfreg ncfce1 ncfce2 ncfoe ncfwe d[31:0]
lh7a404 32-bit system-on-chip 46 advance data sheet figure 27. pcmcia common memory write transfer tova toha tovce1 hclk a[25:0] tovce2 tohce1 tohce2 tovoe tohoe tihd tisd d[15:0] (word) lh7a404-18 ncfreg ncfce1 ncfce2 ncfoe ncfwe d[31:0]
32-bit system-on-chip lh7a404 advance data sheet 47 mmc interface waveforms figure 28 shows the waveforms and timing for an mmc command or data write. figure 29 shows the waveforms and timing for an mmc command or data read. ac97 interface waveforms figure 30 shows the waveforms and timing for the ac97 interface data setup and hold. figure 28. mmc command/data write figure 29. mmc command/data read figure 30. ac97 data setup and hold tovcmd mmcclk mmccmd mmcdat tohcmd tovdat tohdat lh7a404-19 tiovcmd mmcclk mmccmd mmcdat tihcmd tisdat tihdat lh7a404-20 tovac97 ac97sync ac97out ac97in tisac97 tihac97 tohac97 lh7a404-21
lh7a404 32-bit system-on-chip 48 advance data sheet reset, clock, and power controller (rcpc) waveforms figure 31 shows the behavior of the lh7a404 when coming out of reset or power-on. figure 32 shows external reset timing, and table 6 gives the timing parameters. note: *vddc = vddcmin table 6. reset ac timing parameter description min. typ. max. unit tosc (32 khz) oscillator st abilization time after power up (vddc = vddcmin) 550 ms tosc (14 mhz) oscillator stabilization time after power up (vddc = vddcmin) 2.5 ms trstiw nresetin pulse width (once sampled low) 2 hclk trstov nresetin low to nresetout valid (once nresetin sa mpled low) 3.5 hclk trstoh nresetout hold relative to nresetin high 1 hclk figure 31. pll start-up figure 32. external reset lh7a404-22 tosc vddc vddcmin xtal nreseti lh7a404-23 trstiw nreseti
32-bit system-on-chip lh7a404 advance data sheet 49 dc/ac specificat ions (industrial) to be determined.
lh7a404 32-bit system-on-chip 50 advance data sheet package specifications figure 33. 324-ball pbga package specification 1.00 ref. 1.00 19.50 +0.70 -0.05 19.50 +0.70 -0.05 +0.07 -0.13 7.35 5.17 7.35 5.17 16.15 max. 16.15 max. side view top view bottom view (324 solder balls) 1.00 ref. 0.50 r, 3 places note : dimensions in mm. z ca c b 0.30 m 0.63 0.10 m z 0.15 1.17 0.05 0.50 0.10 2.23 0.21 seating plane 0.56 0.06 b a1 ball pad corner 15 13 11 9 7 5 20 19 17 3 a b c d e f g h j k l m n p r t u v w y aa ab 1 16 30 ? typ. 14 12 10 22 20 18 8 6 4 2 a (4x) 0.20 z 0.25 z 0.35 23.00 23.00 324-ball pbga a1 ball pa d corner a1 ball pad indicator, 1.0 dia. available marking area 45 ? chamfer 4 places 324pbga
lh7a404 32-bit system-on-chip ?2002 by sharp corporation reference code sma02004 specifications are subject to change without notice. suggested applications (if any) are for standard use; see important restrictions for limitations on special applications. see l imited warranty for sharp?s product warranty. the limited warranty is in lieu, and exclusive of, all other warranties, express or impl ied. all express and implied warranties, including the warranties of merchantability, fitness for use and fitness for a particular purpose, are specifically excluded. in no event will sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage. north america europe japan sharp microelectronics of the americas 5700 nw pacific rim blvd. camas, wa 98607, u.s.a. phone: (1) 360-834-2500 fax: (1) 360-834-8903 www.sharpsma.com sharp microelectronics europe division of sharp electronics (europe) gmbh sonninstrasse 3 20097 hamburg, germany phone: (49) 40-2376-2286 fax: (49) 40-2376-2232 www.sharpsme.com sharp corporation electronic components & devices 22-22 nagaike-cho, abeno-ku osaka 545-8522, japan phone: (81) 6-6621-1221 fax: (81) 6117-725300/6117-725301 www.sharp-world.com taiwan singapore korea sharp electronic components (taiwan) corporation 8f-a, no. 16, sec. 4, nanking e. rd. taipei, taiwan, republic of china phone: (886) 2-2577-7341 fax: (886) 2-2577-7326/2-2577-7328 sharp electronics (singapore) pte., ltd. 438a, alexandra road, #05-01/02 alexandra technopark, singapore 119967 phone: (65) 271-3566 fax: (65) 271-3855 sharp electronic components (korea) corporation rm 501 geosung b/d, 541 dohwa-dong, mapo-ku seoul 121-701, korea phone: (82) 2-711-5813 ~ 8 fax: (82) 2-711-5819 china hong kong sharp microelectronics of china (shanghai) co., ltd. 28 xin jin qiao road king tower 16f pudong shanghai, 201206 p.r. china phone: (86) 21-5854-7710/21-5834-6056 fax: (86) 21-5854-4340/21-5834-6057 head office: no. 360, bashen road, xin development bldg. 22 waigaoqiao free trade zone shanghai 200131 p.r. china email: smc@china.global.sharp.co.jp sharp-roxy (hong kong) ltd. 3rd business division, 17/f, admiralty centre, tower 1 18 harcourt road, hong kong phone: (852) 28229311 fax: (852) 28660779 www.sharp.com.hk shenzhen representative office: room 13b1, tower c, electronics science & technology building shen nan zhong road shenzhen, p.r. china phone: (86) 755-3273731 fax: (86) 755-3273735

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